- Verilog RTL source code for MIPS32 microAptiv UC Core
- Configuration GUI tools with support for CorExtend UDI
- Verification Test Suite and Verification Test Bench
- Synthesis Support - Reference flow scripts for Synopsys tools
- Simulation Models - Cycle-exact simulation model (VMC)
- DFT Support – Tools - Mentor FastScan scripts, Synopsys – DFT Compiler and TetraMAX scripts
- Timing Analysis - Reference STA scripts for Synopsys PrimeTime tools
- Power Analysis - Synopsys PrimeTime-PX scripts
- Documentation – Core datasheet, implementor’s guide, CorExtend UDI examples and other application notes
- Certification Process
3 easy steps to certify MIPS Open™ Cores–
MIPS Open Core package includes Verification Test Suite (VTS) and Verification Test Bench.
- Using these verification materials, (a) verify your MIPS Open Independent Core Implementation (as a Final Netlist) on each manufacturing process you will use for manufacture, and (b) generate VTS Log Results and Netlist Verification Environment. (The verification materials include instructions how you do this.)
- Deliver a copy of the VTS Log Results and Netlist Verification Environment to MIPS Open.
- MIPS Open will review and notify you in writing whether the MIPS Open Independent Core Implementation has passed the compatibility verification process, or failed (together with details of the failure).
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