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MIPS Open FPGA Labs

We are pleased to release MIPS Open FPGA  Labs 1.0. Please note that the last release was designated MIPSfpga 2.0.

MIPS Open FPGA 1.0 includes a series of laboratories to acquaint you with the MIPS Open FPGA(microAptiv UP) core, its memory system, and system-on-chip (SoC) design using MIPS Open FPGA platform on the Nexys A7 (Formerly Nexys4 DDR) FPGA board. A subset of the labs (Labs 1-7 and 9) are also available for Altera’s DE2-115 board. The remaining labs could also be adapted for the Altera platform.

This material is best used in conjunction with material available in such texts as Digital Design and Computer Architecture, 2nd Edition (Harris & Harris, Elsevier, 2012). Learning the fundamentals of digital design, hardware description languages (HDLs), and computer architecture, particularly the MIPS instruction set architecture (ISA) and hardware, will lay the theoretical groundwork for completing the labs provided here.

MIPS Open FPGA 1.0 Labs delves deeper into the microAptiv core and its memory system. By completing these labs, you will not only understand the system and core but also learn how to modify it. These labs assume that you have completed the MIPS Open FPGA Getting Started Guide that is also available from MIPS Open FPGA.


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