MIPS

MIPS Open™
The New Standard in Open Use ISAs

MIPS
Wave Computing © 2019

Stanford Seminar – MIPS Open

Saraj Mudigonda and Majid Bemanian
Wave Computing

During this session, the speakers will provide an overview of Wave Computing's MIPS Open initiative, including details on the program components, how they can be used to design edge SoCs, licensing terms, the design certification process, etc. Mr. Bemanian will also give a demonstration of how to use various program components for real-world example implementations.

Wave Computing released the first MIPS Open program components at the end of March, providing free access to the MIPS RISC architecture without license fees or royalties. The new MIPS Open online environment is live and immediately accessible at www.mipsopen.com. Specific components in the first program release include:

  • MIPS Instruction Set Architecture: A downloadable copy of the latest version of the MIPS 32/64-bit ISA, SIMD, DSP, Multithreading and Virtualization
  • MIPS Open Toolsi: Integrated Development Environment for embedded real-time operating systems and Linux-based systems for embedded products
  • MIPS Open FPGAs: A complete training program including labs, SoC tutorials and sample (non-commercial) RTL code
  • MIPS Open Cores: low power, low footprint microAptiv Microprocessor(MPU) and Microcontroller (MCU) cores targeted for embedded applications
Historical Note

The MIPS Architecture and processor was originally developed in the Computer Systems Laboratory at Stanford by a team headed by John Hennessey. MIPS and the UC Berkeley developed SPARC archicture were quintessential RISC architectures: influential, popular, and heavily studied.

Date And Time

May 1, 2019