Header Message

This topic contains 11 replies, has 2 voices, and was last updated by  ali 1 month, 4 weeks ago.

Viewing 12 posts - 1 through 12 (of 12 total)
A
ali
Participant
#119595

hi
anybody knows how to put cpu core force to sleep by using UDI interface ?

Hi Ali,

The UDI can stall the pipeline using the UDI_stall_m signal but the core will still be “awake” just waiting for the UDI module to allow the pipeline to flow. The problem with this approach is that the core cannot be awakened until the UDI module allows it or a hard reset occurs. An interrupt or NMI cannot be processed until the pipeline is moving.

The core can be placed into sleep mode by executing the “wait” command. Then an interrupt, NMI, or reset can wake up the core.

Did this help you?

Dan

A
ali
Participant
#119598

thank you for answering
i need your help
i need to tamper with the core code to simulate the effect of a hardware trojan on the core and see if the effect could be observe on the hardware performance counter. for example i need to force the pipeline to issue NOP all the time. how can i do that ? can it be done using UDI interface ?

Ali,

By stalling the UDI module from responding, you are effectively sending NOPs (or stall bubbles) into the pipeline. Since the clock is still running without any instructions being graduated, the cycle count is advancing, while instruction count is not.

The same effect can be gotten from doing an external read to a VERY slow responding address, if the next instruction requires that read data, the pipeline will stall waiting for the read response.

By the way software NOPs are counted as instructions and would be counted in the Instruction count.

Did this help?

A
ali
Participant
#119602

ok thank you
what is the exact code to stall the UDI ?
and another question. how can i handle the interrupts enable signal with UDI?

thank you for answering

Ali,

UDI (User Defined Instruction) module, as explained in the MIPS Open FPGA Labs – Lab19_CorExtend documentation, allows a user to add software functionality to the existing MIPS instruction set. You need to design the module to do what you want to do. In this case, it sounds like generating stalls to the core for some length of time. You might implement a counter in the UDI module that while counting to a specific value drives the stall signal. It could release the stall signal when the counter completes.

Interrupt enable is done by a write to the CP0 Status register, IE bit[0]. Interrupts are not controlled by the UDI module. Also while the stall condition exists, the pipeline is not moving, so interrupts cannot be processed until the pipeline is moving again.

Hope this helped.

A
ali
Participant
#119604

i try to do this. but in mean time i think the library mipsfpga_const is missing from the core.
i getting this msg when trying to compile the project in quartus.

Error (10481): VHDL Use Clause error at m14k_udi_seleqz_nand.vhd(75): design library “work” does not contain primary unit “mipsfpga_const”. Verify that the primary unit exists in the library and has been successfully compiled.

Ali,

The file name is conveniently hidden inside the MIPS_Open_GSG_1.0\rtl_up\VHDL_Files\mfp_ahb_const.vhd file.

A
ali
Participant
#119606

hi i wrote this code in order to stall the core whenever register $t4 is equal to 1 but it doesn’t work. can you tell me why ?

——————————–UDI code—————————————–
process(UDI_gclk,UDI_rs_e)
begin
if (UDI_gclk’event and UDI_gclk=’1′) then
if ((to_integer(unsigned(UDI_rs_e)) = 1)) then

UDI_stall_m <= ‘1’;

else
UDI_stall_m <= ‘0’;
end if;
end if;

end process;

——————————————-assembly code that i load to core ———————————–

asm volatile
(
” li $t3, 2;” // Initialize first source operand
” li $t4, 1;” // Initialize second source operand
” li $t5, 0;” // Initialize destination operand
” nop;” // Avoid RAW dependencies
” UDI1 $t4, $t3, $t5, 0;”
” b .;” // Stay here
” add %0, $t5, $zero;”
: “=r” (x)
);

A
ali
Participant
#119607

i guess my question is that how i can pass value from assembly program to udi interface to use for trigger

Ali,

“i guess my question is that how i can pass value from assembly program to udi interface to use for trigger”

You really can’t. The core is stopped while waiting for a stall to be finished before it can read the next instruction. If you want the UDI module to stall the pipeline, it must be doing that internally. No external event will change that. That is why I suggested an internal timer function. The clock is still running so a down counter will work in the module.

If you build a udi command that waits for an amount of time, then when the command is seen, it will do that. No other intervention is needed.

A
ali
Participant
#119609

isn’t the registr value past from assembly to udi ? how else you perform a operation ? for example for nand operation you pass 2 value to register t3 and t4 then you perform nand with udi interface

Forums are currently locked.