Hi, I downloaded the core project microAptiv Microprocessor Core. When trying to compile it in Quartus, the compiler reports that it cannot find the file m14k_config.vh.
Does the project really not contain a file m14k_config.vh? Or am I not correctly collecting the project?
Best regards, Alex.
The m14k_config.vh file is generated when you run the GUI configuration tool, mipsconfig. A directory will be created in your project directory using the config name you specify and the choices you make in the tool will select the correct modules to be used in the synthesis and simulation of your design. The Package & Simulation Flow document, MD00943, Appendix A (“Example procedure for Installation. Configuration, and Simulation”) will walk you through the recommended procedures.
Once you have created and saved your configuration, the m14k_confog.vh file can be copied into your tool.
With the help of the GUI configuration tool we managed to create a project with the necessary settings for the processor core. In the process of debugging, we are faced with the problem of the cache. We created a project with a fixed map mode and a cache size of 2 KB. In the CP0_config register, we enabled caching of the KSEG0 segment and using the CACHE instruction, allowed the caching of KSEG0. When considering the cyclograms of exchanges in the cached memory zone, we found that processor, when reading data at 0x80001000 make four consecutive readings at 0x80001000 – 0x80001004 – 0x80001008 – 0x8000100С. When re-reading at the same address (0x80001000), processor repeats four consecutive readings at the addresses 0x80001000 – 0x80001004 – 0x80001008 – 0x8000100С.
What needs to be done for the correct settings of the cache?
Can you send an example with setting and working the cache in fixed map mode?
Best regards, Alex.
FMT does not have any effect on the caches, only the type of memory management being used. It does support caches in the following segments, kseg0, kseg2 and kseg3 (assuming you enabled them in the CP0 Config register). You state that you enabled the config.K0 bit and used the CACHE instruction. One thing to note is that the caches are powered up in an undefined state. Unless you are in an FPGA which automatically fills the memories with zeros following a reset. In an actual SOC you would need to initialize the caches to an invalid state (using the Index Invalidate function) clearing the Dirty and Valid bits.
If you haven’t pre-loaded the data (and set the Valid bits) then the first access to the outside memory will start at the requested word of data, then fill in the remainder of the cache line with the next data addresses. The addresses you are seeing is the first 4 words of the cache line. If you try read these lines after the cache line fill, then you shouldn’t see the external accesses, since a cache hit will have occurred.