A core with a cache controller and a Memory Management Unit (MMU) to facilitate embedded systems designs executing rich operating systems which manage virtual memory.
The microAptiv cores are enhanced with the addition of the MIPS DSP Application Specific Extension (ASE) release 2. microAptiv cores also include the microMIPS code compression ISA and MCU ASE which deliver real-time performance and cost advantages in the development of microcontroller and embedded systems designs.
The DSP ASE r2 provides the microAptiv MCU core with high-performance, single-cycle throughput DSP and SIMD capabilities to address the requirements of a broad range of embedded applications requiring more signal processing functionality. These applications include industrial/motor control, smart meters, automotive, storage, mobile communications and security.
In addition, the microAptiv MCU core integrates a memory protection unit and a secure debug functionality, features that can be used to advantage in systems requiring a high level of security.
microAptiv cores offer a significant amount of configurability, including the choice of operating in MIPS32-only mode, MIPS32+microMIPS mode or microMIPS only mode.
The debug capabilities of the microAptiv cores have been further enhanced with the addition of a low-cost 2-wire cJTAG option (IEEE standard 1149.7).